1. Field of the Invention
The present invention relates to a differentiating circuit for generating differential signals for an NRZ (Non Return to Zero) data signal, and to a clock generating circuit for generating a clock signal from the differential signal. This differentiating circuit can be used, for example, in a doubler for doubling a reference clock signal or a timing recovery circuit for recovering a clock component from input data, for optical transmitters or optical receivers of optical communication systems.
2. Description of the Related Art
Generally, in optical communication systems, an optical transmission terminal is provided at one end of an optical transmission path, a plurality of low transmission rate circuits are time division multiplexed, and an optical signal having a higher transmission rate is transmitted to the transmission path. This time division multiplexing is usually carried out with a reference clock signal supplied to an optical transmitter, based on a clock signal that has been multiplied in accordance with a clock signal having a transmission rate of an optical signal sent to the optical transmission path. In order to multiply the clock signal, a differential waveform of the reference clock signal is generated and this differential waveform must be rectified.
Also, in an optical receiver, when logic levels and jitter of an input digital signal are identified and reproduced, this is usually carried out by latching an equalized clock signal using a specified clock signal. If the input data signal is a signal containing a clock component such as RZ (return to zero) code, a clock component can be easily extracted by passing the signal through a filter.
However, recent coding structures for the input data signal have been standardized towards NRZ (Non Return to Zero) code, and a circuit for differentiating this input data signal has become necessary in order to recover a clock component.
FIG. 1 is one example of a clock generating circuit of the related art. FIG. 2 is a signal waveform drawing for all parts of the clock generating circuit of FIG. 1. The clock generating circuit shown in FIG. 1 has a conventional differentiating circuit 10, a rectifying circuit 2, and a resonance circuit 3. The differentiating circuit 10 comprises a differential input buffer 11 to which the NRZ data signal S1 is differentially input, a delay circuit 12 in which the designed delay time is 1/2 of the length of a data hold period of the NRZ data signal, and a buffer 13. The rectifying circuit 2 comprises a non-linear circuit 21 for carrying out full-wave rectification of a differentiation signal generated in the differentiation circuit 10, and a buffer 22. Finally, the resonance circuit 3 comprises a resonator 31 resonating at a frequency having a period of the data hold period length of the NRZ data signal and an output buffer 32.
The differentiating circuit 10 has all components except the delay circuit 12 arranged on a single semiconductor substrate (not shown), and only the delay circuit 12 is attached externally. The delay circuit 12 is formed using a strip line. Further, a non-inverted NRZ data signal S2a and an inverted NRZ data signal S2b that have been generated in the buffer 11 are respectively delayed by the delay circuit 12, these delayed signals are respectively added to signals of the other side, and the resonator 31 generates the differential signal from the resultant signals.
Specifically, the signal S2ab which is the inverted NRZ signal S2b delayed is added to the non-inverted NRZ data signal S2a, and a differential signal S3a is generated. (The inverted differential signal S3b is obtained in a similar manner.) This differential signal S3a is full wave rectified by the non-linear circuit 21 and in this way a rectified signal S7a including a clock frequency component is generated. A clock signal S9a is generated by driving the resonance circuit 31 using this rectfied signal S7a. However, in the above described differentiation circuit of the related art, it is extremely difficult to manufacture so that the characteristic impedance of the delay circuit 12 and the output impedance of the differential input buffer 11 are matched.
It is also extremely difficult to manufacture the delay circuit 12 so that the delay time the has the designed value (specifically, a design value of half the period length of the NRZ signal data T0 equivalent to the period of a clock signal to be generated). This means that because of the above-mentioned lack of impedance matching, reflections occur at boundaries between the two components, and with respect to the delay circuit 12, reflections are repeated and resonance occurs at a specified frequency. The base resonant frequency f1[0] of this resonance is different from the clock frequency of the clock signals S9a, S9b, namely it is different from the resonant frequency f CLK of the resonator 31 and approaches fCLK because of manufacturing errors in the above mentioned delay time t1.
A resonant component of the above-mentioned delay circuit 12 is mixed with the differential signal, and part of the signal passes through the non-linear circuit 21 and is input to the resonator 31. Since the frequency f1[0] of the resonant component of the delay line becomes dose to the resonant frequency fCLK of the resonator 31, the resonant component is not removed, even in a resonator 31 with a high Q factor, and is mixed with the clock signal, and there is a problem that the integrity of the clock is lowered.